Implementing an algorithm by modelling an FSM in an HDL

We are going to use Verilog for this project. So, any verilog compiler and simulator should do. Xilinx and ModelSim are really good tools. But since I’m a *nix guy, I’m going to use Icarus Verilog to compile code and gtkwave to view the signal timing diagrams. They are free to use, easy to learn and much more light-weight than other full-fledged options.

In a complex digital system, the hardware is typically partitioned into two parts:

a) Data Path, which consists of the functional units where all computations are carried out. Typically consists of registers, multiplexers, bus, adders, multipliers, counters and other functional blocks.

b) Control Path, which implements a finite-state machine and provides control signals to the data path in proper sequence. In response to the control signals, various operations are carried out by the data path. Also, it takes inputs from the data path regarding various status information.

The state transition is controlled by control path or control unit or controller. The control unit (CU) send all the signals necessary to trigger any operation in data path. The data path consists of elements that process data and addresses. Usually there’s also a clock signal and a data bus that go to both data path and control path. By specifying a particular sequence of operations, the control unit can implement a given algorithm.

The following block diagram shows the idea of separating a system into a data path and a control path:

Multiplication by repeated addition

Algorithm: Multiply (a, b)
Step 1. Get the values for a and b.
Step 2. If (either a = 0 or b = 0) then
Step 3. Set the value of the product to be 0
Step 4. Else
Step 5. Set the value of product to 0
Step 6. While (b > 0)
Step 7. Set the value of…

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